The present invention relates to a buffer using a two-port memory. More particularly, the present invention relates to a buffer with a two-port memory, which aims at a high-speed access time when being used as a buffer.
In the related art, two-port RAMs each having a first port acting as a write port and a second port acting as a read port are quoted. The two-port RAM is used as a buffer that counts up an address value in each port with a corresponding strobe signal, stores sets of data arrived for a given period, and transmits each set of data in the arrival order in accordance with a request.
The RAM includes an address decoder, memory cells arranged two-dimensionally, a signal amplifier circuit corresponding to writing, and a signal amplifier circuit corresponding to reading. The RAM specifies a line of memory cells corresponding to a specific address specified by the address decoder. One of drive lines (called a word line) provided for respective lines of memory cells is activated to select the memory cells on the selected line.
That process is performed by a three-step procedure. That is, the three-step procedure includes the steps of reading an address value from an address register every time a memory cell is accessed, decoding the address until a word line driven from the address value is specified, and driving only one word line to an active state. In the steps, the sum of respective delay times represents an access time to a memory cell.
FIG. 6 is a block diagram illustrating a related-art buffer using a two-port RAM. A memory cell array 10, which includes memory cells arranged two-dimensionally (in a matrix form), forms a storage element area. In order to access a specific memory cell in the memory cell array 10, column selection lines (generally called word lines) and row selection lines (generally called bit lines) are arranged in a matrix form. Generally, one of the word lines is specifically activated by the address provided to the RAM. The associated bit line transmits data provided to the RAM, to a memory cell.
Referring to FIG. 6, the RAM has one read port and one write port. The two-ports can operate simultaneously and independently. The two-port RAM includes n word lines (51_0, 51_1, 51_2, . . . , 51xe2x80x94nxe2x88x921, 51xe2x80x94n) corresponding a write address, n word lines (71_0, 71_1, 71_2, . . . , 71xe2x80x94nxe2x88x921, 71xe2x80x94n) corresponding to a read address, a bit line 21 corresponding to write data, and a bit line 31 corresponding to read data.
FIG. 6 shows one bit line 21 for write data and one bit line 31 for read data. However, there are actually bit lines corresponding to the number of bits. Generally, the differential transmission is performed that transmits one bit using a pair of bit lines for positive logic and negative logic. Actually, the number of bit lines is twice the number of bits.
Next, the operation of the conventional buffer having a two-port RAM shown in FIG. 6 will be explained below.
First, an initial value, being generally all 0 data, is set to the write address register 600. However, a certain value may be set as an initial value to set an offset starting a write operation from a specific address. Here, it is assumed that all 0 data are set to the write address register. Each of the write address decoders (640_0, 640_1, 640_2, . . . , 640xe2x80x94nxe2x88x921, 640xe2x80x94n) decodes the address value set to the write address register 600. Only the address decoder in coincidence with an address value outputs an active result. In the initial state where the address value is of all 0s, only the address decoder (640_0) corresponding to the least significant address outputs an active result.
The word line drivers (50_0, 50_1, 50_2, . . . , 50xe2x80x94nxe2x88x921, 50xe2x80x94n) respectively reinforce the drive capability of the outputs of the write address decoders (640_0, 640_1, 640_2, . . . , 640xe2x80x94nxe2x88x921, 640xe2x80x94n) and then drive the word lines (51_0, 51_1, 51_2, . . . , 51xe2x80x94nxe2x88x921, 51xe2x80x94n). Actually, only the word line connected to the address decoder outputting an active result is driven. In an initial state, only the word line (51_0) driven by the word line driver (50_0) corresponding to the least significant address becomes a valid selection state.
On the other hand, the write data stored in the write data register 20 is sent to each memory cell through the bit line 21. In the initial state, since the word line (50_0) corresponding to the least address is in a selection state, the data in the write data register 20 is written into the memory cell of the least significant address.
The incrementer 601, connected to the output of the write address register 600, counts up the address. The count-up address value is again fed back to the input of the write address register 600. The write address register 600 captures the count-up address only when the strobe signal 42 is in an active state. When the strobe signal 42 is not an active state, the write address register 600 continues to hold the counted-up value. Therefore, only when the strobe signal 42 is in an active state, the write address value is counted up. At the same time, the strobe signal 42 controls the data capture to the write data register 20. Simultaneously when the write address value is counted up, a new write data value is captured into the write data register 20.
In doing so, when the strobe signal 42 is in an active state, the write address value is counted up. As a result of address decoding, the word line driven to an effective selection state is sequentially changed in the increasing order from the least significant address. At the same time, since the write data is updated sequentially, newer write data is stored into an upper address. At the time when the write address value becomes an all xe2x80x9c1sxe2x80x9d state, the status reaches the most significant address. Thereafter, when being counted up with the strobe signal, the write address value is reset to an all xe2x80x9c0sxe2x80x9d state, so that the data of the least significant address is overwritten. Thus, the ring data buffer that can store sets of data corresponding to the number of addresses of the RAM is configured.
That is also the case for the operation of the reading side. After the address value stored in the read address register 650 is decoded by the read address decoders (660_0, 660_1, 660_2, . . . , 660xe2x80x94nxe2x88x921, 660xe2x80x94n), the word lines (71_0, 71_1, 71_2, . . . , 71xe2x80x94nxe2x88x921, 71xe2x80x94n) are respectively driven through the word line drivers (70_0, 70_1, 70_2, . . . , 70xe2x80x94nxe2x88x921, 70xe2x80x94n). As a result, data in the memory cell of a corresponding address is read out and is input to the read data register 30 through the bit line 31. The incrementer 651, connected to the output of the read address register 650, counts up the read address. When the strobe signal 62 is in an active state, the incrementer 651 updates the content of the read address register 650 and the content of the read data register 30. In doing so, when the strobe signal is in an active state on the reading side, the data stored in the memory cells are sequentially read out to upper addresses from the least significant address. After the data of the most significant address is read out, the operation returns to the least significant address to read data again.
As described above, in the operation of the conventional buffer using a two-port memory, the writing side is first operated to store data to memory cells. After it is ascertained that data have been stored until a specified address, the operation of the reading side begins. When the operation of the reading side begins, the buffer is controlled using only the strobe signal 42 on the reading side and the strobe signal 62 on the writing side.
However, in the above-mentioned buffer (with a two-port RAM), only by sequentially counting up the read address or the write address with the strobe signal, the word line to be activated is sequentially changed from the least significant address to the most significant address. The problem is it is inefficient to provide address decoders corresponding to word line drivers, which are activated sequentially.
Moreover, the conventional buffer has the problem in that the time period for reading an address value from the address register and then driving the word line after address decoding is taken largely.
Moreover, in the conventional two-port RAM, the address signal must be decoded every time the address is counted up by a strobe signal. For that reason, the problem is that the power consumed by the address decoders becomes wasteful.
The present invention is made to solve the above-mentioned problems. An object of the present invention is to provide a buffer using a two-port memory, which has a high-speed access time and which can operate with reduced power consumption.
In an aspect of the present invention, a buffer using a two-port memory comprises a memory cell array formed of memory cells arranged two-dimensionally in a matrix form; a plurality of write-word lines arranged corresponding to a write address; a plurality of read-word lines arranged corresponding to a read address; a plurality of write bit lines arranged corresponding to write data; a plurality of read bit lines arranged corresponding to read data; a plurality of word line registers arranged corresponding to either the write word lines or the read word lines; a plurality of word line drivers respectively connected directly to outputs of the word line registers, for respectively driving the word lines; a write data register connected to the write bit lines; and a read data register connected to the read bit line; the word line registers being mutually cascaded in a ring form, to receive a strobe signal; whereby each of the word line registers counts up its input when the strobe signal is in an active state and holds a current value when the strobe signal is not in an active state.
In another aspect of the present invention, a buffer using a two-port memory, comprises a memory cell array formed of memory cells arranged two-dimensionally in a matrix form; a plurality of write-word lines arranged corresponding to a write address; a plurality of read-word lines arranged corresponding to a read address; a plurality of write bit lines arranged corresponding to write data; a plurality of read bit lines arranged corresponding to read data; a plurality of write word line registers arranged corresponding to the write word lines; a plurality of read word line registers arranged corresponding to the read word lines; a plurality of write word line drivers for directly receiving outputs of the write word line registers, for driving the write word lines; a plurality of read word line drivers for directly receiving outputs of the read word line registers and driving the read word lines; a write data register connected to the write bit lines; and a read data register connected to the read bit line; the write word line registers being mutually cascaded in a ring form, to receive a write strobe signal; whereby each of the write word line registers counts up an input when the write strobe signal is in an active state and holds a current value when the write strobe signal is not in an active state; the read word line registers being mutually cascaded in a ring form, to receive a read strobe signal; whereby each of the read word line registers counts up an input when the read strobe signal is in an active state and holds a current value when the read strobe signal is not in an active state.
In the buffer according to the present invention, the write strobe signal is used to controllably update the write data register. The read strobe signal is used to controllably update the read data register. The write data register updates write data when the write strobe signal is in an active state. The read data register updates read data when the read strobe signal is in an active state. The write data register hold a current value when the write strobe signal is not in an active state. The read data register hold a current value when the read strobe signal is not in an active state.
In the buffer according to the present invention, a write word line register corresponding to a specific address receives a write START signal as a synchronous set input. A read word line register corresponding to a specific address receives a read START signal as a synchronous set input.
According to the present invention, the buffer further comprises a write address initial value register for storing a write address initial value; a write address initial value decoder for decoding a write address initial value stored in the write address initial value register; a plurality of AND logic circuits for creating a synchronous set signal to the write word line register in accordance with plural decode addresses from the write address initial value decoder and in accordance with a write START signal; a read address initial value register for storing a read address initial value; a read address initial value decoder for decoding a read address initial value stored in the read address initial value register; and a plurality of AND logic circuits for creating a synchronous set signal to the read word line register in accordance with plural decode addresses from the read address initial value decoder and in accordance with a read START signal.
According to the present invention, the buffer further comprises a write delay register, which forms a leading edge differentiation circuit, for detecting rising when a write word line register of a most significant address is in an active state and then creating one clock pulse; an AND logic circuit with write negative inputs, having an inversion input terminal which receives an output of the write delay register and a normal input terminal which receives an output of the write word line register of the most significant address; a write exclusive OR logic circuit forming a write address carry flag for toggling one clock pulse as an input; a write flag register for receiving an output of the write exclusive OR logic circuit; a read delay register forming a read differentiation circuit that detects rising when a read word line register of the most significant address becomes an active state and then creates one clock pulse; an AND logic circuit with read negative inputs, having an inversion input terminal for receiving an output of the read delay register and a normal input terminal for receiving an output of the read word line register of the most significant address; a read exclusive OR logic circuit forming a read address carry flag toggling one clock pulse as an input; a read flag register for receiving an output of the read exclusive OR logic circuit; a plurality of coincidence detection AND logic circuits each for detecting whether or not a value held in each write word line register coincides with a value held in each read word line register; an OR logic circuit for detecting whether or not there is a coincidence result in any one of the coincidence detection AND logic circuit; an exclusive OR logic circuit and an AND logic circuit, for detecting a buffer overflow when a write address carry flag is not in coincident with a read address carry flag and when the OR logic circuit produces a coincidence result; and an exclusive NOR logic circuit and an AND logic circuit, for detecting a buffer underflow when a write address carry flag is in coincident with a read address carry flag and when the OR logic circuit produces a coincidence result.
According to the present invention, the importance of the fact that the write address and the read address are counted up with the strobe signal is recognized in the method of using a two-port RAM as a buffer. Thus, the address decoders (each acting as a RAM) in the two systems used in the prior art are removed. Conventionally, the access time to the buffer, during which data is read by accessing a RAM cell from the address register via the address decoder, is required. However, in the present invention, the delay time in the address decoder is cut, so that the buffer can realize its high-speed operation.
Moreover, the present invention can reduce the power consumption of the address decoder, thus operating the entire system with reduced power. Several buffers or tens of buffers are often used per specific chip. In such a case, the buffer according to the present invention can effectively reduce the power consumption per chip.